[slinkelist] Parallel Port Timings

[Nirvis Help (Colby)]

> -----Original Message-----
> From: slinkelist-admin@nirvis.com [mailto:slinkelist-admin@nirvis.com]On
> Behalf Of thomasdr@us.ibm.com
> Sent: Wednesday, March 22, 2000 12:13 PM
> To: slinkelist@nirvis.com
> Subject: [slinkelist] Parallel Port Timings
>
>
>
>
> Does anyone know the parallel port timing requirements?
>
> For example, how much setup time exists between DOSTB rising and
> data being
> valid on the DIO pins (if the direction is output).  Or should I use the
> negative edge of DOSTB to latch the data on the DIO lines into external
> devices?

I'd probably have to look with a scope to be sure, but DOSTB should go low,
then the data should appear about 1us later. About 1us after that DOSTB goes
high, and this is when you should latch the data.


>
> Maybe I can use the DIO lines as bidirectional lines instead of dedicating
> some to inputs and some as outputs.  I'm thinking of using DOSTB
> to control
> when the external logic is driving the DIO lines.  DOSTB high, tri-state
> external drivers, DOSTB low, OK to drive the DIO pins and pulse DISTB to
> initiate a message back to the PC.
>
> In this case, DOSTB needs to go high BEFORE the SLINK drives the
> DIO lines.
> Can I count on this?  Or do I need to use another DIO line as an
> output for
> the sole purpose of controlling the direction (tri-state vs. driving) of
> the external logic.
> In this case I'd first toggle the "ENA" DIO line to turn off the external
> drivers (to prevent bus contention) then change the direction of the
> remaining DIO lines to outputs.
>
> After writing the data from the SLINK to the external logic, the SLINK
> could turn the DIO back around to be inputs (and allow the external logic
> to drive the DIO lines by asserting the "ENA" DIO line) or perhaps the
> external logic could ask the SLINK to get off the DIO bus by asserting the
> DISTB  (which would initiate a message back to the PC code) .  The PC code
> then turns the direction of the DIO lines to inputs.
>
> What's the best way to do this?  Has anyone already done this?  (Expand
> SLINK parallel port with external logic).
>

Communications in this way may be slow and awkward. It may be easier just to
create an S-Link device using a FPGA and connect it that way.

Colby